icarus verilogでGate Level Modeling


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gate level modeling

gatelevel.v

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module gates (
input a_input,
input b_input,
output c_and,
output d_or,
output e_xor
);
and (c_and, a_input, b_input); // c is the output, a and b are inputs
or (d_or, a_input, b_input); // d is the output, a and b are inputs
xor (e_xor, a_input, b_input); // e is the output, a and b are inputs
endmodule


gatelevel_test.v

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module gatelevel();
//input
reg a;
reg b;
// output
wire c;
wire d;
wire e;
gates uut (
.a_input(a),
.b_input(b),
.c_and(c),
.d_or(d),
.e_xor(e)
);
integer i;
initial begin
a = 0;
b = 0;
end
initial begin
for (i=0; i<20; i=i+1) begin
#1 a <= $random;
b <= $random;
end
end
initial begin
// #200 $finish();
$monitor("t=%0t, a=%0b, c=%0b, c(and)=%0b, d(or)=%0b, e(xor)=%0b \n", $time, a, b, c, d, e);
$dumpfile("gatelevel.vcd");
$dumpvars(0, gatelevel);
end
endmodule // gate

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