Icarus Verilog でFizzBuzz

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• Icarus Verilogをやってみた
• FizzBuzzっぽいものをかいてみた
• こんな感じか?

mytest.v

module mytest(fizz,buzz);
    input fizz, buzz;
    output out, fizzbuzz;
    assign out = ~fizz & ~buzz;
    assign fizzbuzz = fizz & buzz;
endmodule

mytest_test.v

module top();
    wire out;
    reg a,b;

    mytest mytest_instance(a,b);

    initial begin
        a = 0;
        forever begin
            #2 a=~a;
            #1 a=~a;
        end
    end

    initial begin
        b = 0;
        forever begin
            #4 b=~b;
            #1 b=~b;
        end
    end

    initial begin
        #100 $finish();
    end

    initial begin
        $dumpfile("mytest_test.vcd");
        $dumpvars(0, mytest_instance);
    end
endmodule

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